The present invention relates, in general, to methods and apparatus for managing power usage in a computer system with multiple processors.
A large number of computer systems today contain many processing units that may be employed on one task or many different tasks. The advent of the Internet has led to large xe2x80x9cserver farmsxe2x80x9d where buildings house a very large number of processing units that are partitioned into racks of processing units (e.g., servers) where each rack has power distribution and cooling distribution capabilities. The processing units in the racks may be self-contained with fans and their own power supplies. Typically, more self-contained processing units may be placed in a rack than the corresponding cooling system for the rack can cool if all processing units were operating such that they dissipated maximum power. The building that houses these many racks of processing systems may also house more racks than the corresponding building cooling system can cool if all racks were operating at some high level of power dissipation even though each rack may be within its cooling limits. The cooling limit of the building may depend on the outside weather and the status of the building cooling system.
Within the racks, each self-contained processing unit (e.g., server) may have one or more printed circuit boards that may include multiple very large scale integrated circuits (VLSI) as the processing units. The processing units in a rack may themselves have thermal limits or other limits depending on how intensively the multiprocessor VLSI chips are utilized. In fact, the individual VLSI chips may also have a marked difference in temperatures if they are utilized differently for particular tasks.
Realizing that managing power within a VLSI chip may be a problem, chip designers have been designing capabilities into VLSI circuits that allow the power dissipated in the chip to be managed. The power dissipation in a VLSI chip employing complementary metal oxide semiconductor (CMOS) circuits is proportional to the square of the voltage excursions on the logic circuits and linearly proportional to the frequency at which the logic circuits operate. Some VLSI chips have been designed to allow the VLSI power supply voltage and the clock frequency to be modified depending on the task to be performed by the VLSI chip and its operating temperature. Many VLSI processor chips incorporate chip temperature sensing as part of the overall chip design to allow chip temperature to be easily monitored. Some prior art processors employ algorithms that allow the chip""s temperature to be used in an overall strategy for chip power management where both the chip voltage and clock frequency are simultaneously modified in a prescribed manner. These VLSI processors monitor instruction execution and determine an optimum chip clock frequency and power supply voltage to use to allow the VLSI processor to execute a given instruction set more efficiently than alternate designs.
Recent advances in VLSI processor chips have allowed VLSI chips to have multiple processors on one chip, further increasing the possible VLSI chip power dissipation. These multiple processors may be employed in a wide range of applications where processor utilization may require power management to conserve VLSI chip power or prevent a VLSI chip failure.
When xe2x80x9cserver farmsxe2x80x9d employ servers with VLSI processor chips where groups of chips or single chips may implement multiple processors, power and performance management at the chip, server, rack and building level, required to meet the needs of diverse users, becomes more complex. The building housing the server farm may have severe power density issues which do not allow all its racks of servers to be operated at their maximum performance. While actions of prior art power management may improve the power density of the building, the needs of the users would not necessarily be met with the best cost versus performance. Many of the power management issues facing large server farms, single servers employing multiple processors in a business environment, and even VLSI processor chips with multiple processors, require consideration of other parameters besides the temperature of VLSI chips or system components.
There is, therefore, a need for a power and performance management method and control system that may be applied to individual multiprocessor VLSI chips, multiprocessing systems, and buildings housing a large number of multiprocessing systems where physical as well as operational parameters may be employed to optimize the cost, performance, quality of service, and environmental aspects of data processing.
A multiprocessor (MP) system management controller receives inputs defining the tasks to be performed as well as policy parameters and quality of service parameters. Processing is allocated to processors in the MP system based on the tasks, quality of service and policy parameters. A determination is made as to workload distribution by allocating processors to work on specific tasks. MP system parameters, including voltages, clock frequencies, cooling outputs, and setting processors units into various types of sleep modes. Various sensors measure the system local and global output responses to these parameter variations. These output responses are compared to the power and performance goals set by the MP system management controller to meet cost of power, quality of service, thermal, and various other system performance goals.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.